工作簽證因為大部分的前輩都從EP待到變成公民，EP數量還很多
歡迎各路英雄好漢，想出國看看的都來試試呀
有興趣的夥伴們可以私我細聊，或者私我履歷唷！
【JD】
Roles & Responsibilities
Responsibilities
Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
Verify Logic at ISP level and Digital System level
Optimize Design for less gate count and low power consumption
Drive ISP Design activities in close collaboration with ISP Algorithm Team
Requirements
Minimum MSEE, or BSEE, or related/equivalent discipline
Experience / knowledge in RTL, C/C++ programming and verification
Strong debugging and problem-solving skills
Good communication and interpersonal skills
Results-oriented and adaptable to changes
C++/SystemC knowledge with High Level Synthesis experience is a plus.
Experience / knowledge in CMOS Image Sensor is a plus
